2022, Vol. 2, Issue 1, Part A
Review paper on low power VLSI design techniques
Author(s): Zaid Siddiqui
Abstract: In the modern field of online industries, one of the most prominent trends that has evolved is a focus on using less power. In the design of VLSI chips, leakage current has risen to the level of importance formerly reserved for throughput and area. Because of the growing complexity, decreasing power usage and overall energy management on chips are the primary problems below 100 nanometers. This is because technology is shrinking. Because of the necessity to cut down on packaging costs and increase battery life, several designs place a significant emphasis on optimizing power consumption in addition to timing.Inductance plays a crucial role with low wattage VLSI designs, not just for power usage and for power usage. The amount of power that is lost due to integration circuits' overall power loss is becoming more critical, with leakage current playing an increasingly significant role. This article provides an overview of the many power management methods, approaches, and techniques that may be used to low power circuitry. The future obstacles that should be overcome in order to create circuits with low power consumption and fantastic performance are indeed mentioned.
Pages: 10-15 | Views: 584 | Downloads: 278
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How to cite this article:
Zaid Siddiqui. Review paper on low power VLSI design techniques. Int J Electron Microcircuits 2022;2(1):10-15.
