2025, Vol. 5, Issue 1, Part A

Using the Cadence Virtuoso Design Suite, the oscillator was first modeled at the schematic level, followed by layout design and post-layout parasitic extraction using Assura tools. Simulations were conducted at two supply voltages (0.9 V and 1.2 V) and three temperatures (25°C, 50°C, and 75°C). The results demonstrated a clear trade-off between power consumption and performance: the oscillator achieved a maximum frequency of 148.7 MHz at 1.2 V and 25°C and a minimum power consumption of 12.4 µW at 0.9 V and 25°C, with jitter values ranging from 1.6 ps to 2.8 ps. A two-way ANOVA confirmed that supply voltage had a statistically significant effect on both frequency and power consumption (p < 0.001), while temperature had a secondary but notable impact (p < 0.05), with no significant interaction effect.

The study concludes that careful transistor sizing, voltage optimization, and simulation-driven layout design using Cadence Virtuoso can result in a highly efficient and stable ring oscillator suitable for integration in modern VLSI systems. The findings offer valuable insights for designing low-power clock generation and sensor systems, with practical recommendations for future circuit implementations in energy-constrained applications.